High-speed data communication systems have a need for improved maintenance of primary clock timing and synchronization of data carried by high-speed data buses. In a co-pending Patent Application entitled "Parallel Data Bus Integrated Clocking and Control" by John Gordon Hogeboom and assigned to Northern Telecom Limited, a high-speed parallel data bus having a single integrated signal path carrying both synchronous clock information and control data is disclosed. In this invention, the clock signal is transmitted at a lower rate, and only a primary edge, for example the falling edge, is used to control the timing of a phase-locked loop (PLL), which can then regenerate all required equal or high-rate clocks with required stability and phase relations. By using only timing increments of one bit time for the clock signal high and low periods, the same transmission media and interfaces may be used for the clock as are normally used for the associated data stream or streams. Furthermore, the alternate edge of the signal is independently modulated in increments of one data bit time to carry control data. Control data transmitted in this way, integrated with the clock signal, may be used in a process of adjusting or "trimming" delays of data from two or more sources multiplexed onto a data line. At the receiving end of the bus, the delays are adjusted in accordance with the control data, so that the various multiplexed data streams will align with each other in time at data receivers used to recover the bit streams. The clock signal is an ideal signal to carry such control data, since it must already connect to all transmitters and receivers, and because it directly provides the timing information needed to optimally recover the data it carries. In summary, the invention by John Gordon Hogeboom provides efficient means for achieving both a synchronous clock and a control data channel in a single signal path used with a high-speed parallel data bus, where the bus is implemented in a more compact and flexible manner than existing buses and achieves the maximum speed capability and/or the maximum margins for a given speed requirement.
An important issue for such a high-speed data bus is the transmission delays which occur both internally and externally to the bus itself. The term "entrainment" refers to the sampling and comparing of data which takes place at both the transmitting and receiving ends of the bus in order to regulate these delays and ensure the correct alignment of the data. For example, assume that 8 sources, each receiving 4 serial bits and outputting a 4 bit wide bus, all output their data at what they believe is the same time in order to form a 32 bit wide data bus. The correct format for the output over 6 clock cycles is:
S1 S2 S3 S4 S5 S6 S7 S8 cc1 0000 0000 0000 0000 0000 0000 0000 0000 cc2 0000 0000 0000 0000 0000 0000 0000 0000 cc3 0000 0000 0000 0000 0000 0000 0000 0000 cc4 1111 1111 1111 1111 1111 1111 1111 1111 cc5 0000 0000 0000 0000 0000 0000 0000 0000 cc6 0000 0000 0000 0000 0000 0000 0000 0000
Unfortunately, due to circuit board routing and varying environmental conditions, such as temperature, over time the 32 bits may become out of step with each other. Some of the bits may be early, while others may be late. The sampled and merged 32 bit bus may look like the following instead:
 S1 S2 S3 S4 S5 S6 S7 S8 cc1 0000 0000 0000 0000 0000 0000 0000 0000 cc2 0000 0000 0000 0000 0000 0000 0000 0000 cc3 0000 0001 0000 0000 0000 1100 0000 0000 cc4 0011 1110 1111 1011 1110 0011 1110 1111 cc5 1100 0000 0000 0100 0001 0000 0001 0000 cc6 0000 0000 0000 0000 0000 0000 0000 0000
It is through entrainment that this incorrectly timed output can be realigned into the correct format.
The entrainment takes place at the hardware devices which use the high-speed data bus to transmit and receive data, for example a chip on an integrated circuit board, whereby such a device must include multiple high-speed connections. In general, for each high-speed connection, a bidirectional data pad cell within the hardware device is capable of both transmitting data to and receiving data from the connection. In the former case, the data pad cell is also referred to as a driver, whereas in the latter case, the data pad cell is also referred to as a receiver. In order to perform entrainment in the receive direction, the data pad cell must sample incoming data near the center of the data eye pattern. In order to do this, the pad must be able to control the sampling point to within a fraction of a bit time. Typically, the data pad cells of a device do contain such a sampling circuit, controlled by the device core, to allow the bit sample point to be fine grain adjusted. This adjustment consists in shifting the sample point whenever circuit board routing and various environmental factors cause a shift in the incoming data. Unfortunately, existing sampling circuitry lacks the ability to measure and control this adjustment from the core of the terminal device. Without this ability, the entrainment of a high-speed data transmission bus by such a device is much more complex and expensive. A similar situation occurs in the transmit direction.
Existing methods for performing the entrainment of a high-speed data transmission bus include reversing the data bus to return entrainment status, and providing entrainment signaling via a separate bus channel. Unfortunately, such methods have important disadvantages, such as complex hardware which can not be altered once cast in silicon, and the requirement for additional dedicated device I/O pins, to be used only for entrainment control and status feedback.
The background information provided above shows that there exists a need in the industry to provide an improved system and method for entraining a high-speed data transmission bus, in order to correct the data misalignment caused by the internal and external transmission bus delays.